#ifndef __RC8088_H__
#define __RC8088_H__

#include <stdint.h>
#include <string.h>
#include <stdio.h>
#define RC8088_CRC_LEN   2
#define RC8088_REG_LEN                         4
#define RC8088_REG_BANK_SIZE                   612


#define RC8088_Write_REG_SPI_CRC               0x21u
#define RC8088_READ_REG_SPI_CRC                0x25u
#define RC8088_Write_MEM_SPI_CRC               0x22u
#define RC8088_READ_MEM_SPI_CRC                0x26u

#define RC8088_Write_REG_QSPI_CRC              0x31u
#define RC8088_READ_REG_QSPI_CRC               0x35u
#define RC8088_Write_MEM_QSPI_CRC              0x32u
#define RC8088_READ_MEM_QSPI_CRC               0x33u


#define RC8088_DCMD_CLR_ALL                         0x65F981u
#define RC8088_DCMD_CLR_WGEN                        0x576282u
#define RC8088_DCMD_CLR_MIPI                        0x46EB83u
#define RC8088_DCMD_CLR_EDMA                        0x325484u
#define RC8088_DCMD_CLR_FFT                         0x23DD85u
#define RC8088_DCMD_CLR_PREP                        0x114686u
#define RC8088_DCMD_CLR_REG                         0x00CF87u
#define RC8088_DCMD_CLR_MEM                         0xF83888u

#define RC8088_DCMD_TRIG_P10                        0x64F190u
#define RC8088_DCMD_TRIG_EDMA                       0x757891u

#define RC8088_DCMD_REG_CRC_CHECK                   0x5572A0u

#define RC8088_DCMD_WAVE_START                      0x44FBA1u
#define RC8088_DCMD_WAVE_STOP                       0x7660A2u

#define RC8088_DCMD_BIG_ENDIAN                      0x45F3B0u
#define RC8088_DCMD_LITTLE_ENDIAN                   0x547AB1u

/***************************************************/
/*---------------------ANA-------------------------*/
/***************************************************/
typedef struct{
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t rfplldcn:13;
			volatile uint32_t MipiPllLock:1;
			volatile uint32_t VSS1:2;
			volatile uint32_t adplldcn:13;
			volatile uint32_t VSS2:3;
		}BIT;
	} STA00;/*!< Offset: 0x00 (RO)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t adc_oscali:21;
			volatile uint32_t VSS:3;
			volatile uint32_t CHIPID:8;
		}BIT;
	} STA01;/*!< Offset: 0x01 (RO)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t adc_dft:16;
			volatile uint32_t adc_clkcali:16;
		}BIT;
	} STA02;/*!< Offset: 0x02 (RO)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t GPADC1:10;
			volatile uint32_t GPADC2:10;
			volatile uint32_t GPADC3:10;
			volatile uint32_t clkrdy:1;
			volatile uint32_t VSS:1;
		}BIT;
	} STA03;/*!< Offset: 0x03 (RO)*/
	volatile  uint32_t RESERVED0[12];          /*!< Offset: 0x04 (RO)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t enpll:1;
			volatile uint32_t enlofan:1;
			volatile uint32_t enlotx:2;
			volatile uint32_t enrxbb:8;
			volatile uint32_t enrxrf:4;
			volatile uint32_t enlorx:2;
			volatile uint32_t enadc:8;
			volatile uint32_t enmipi:2;
			volatile uint32_t UFT0:4;
		}BIT;
	} CFG00;/*!< Offset: 0x10 (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t envco:2;
			volatile uint32_t UFT0:10;
			volatile uint32_t ct_vcoband:3;
			volatile uint32_t UFT1:13;
			volatile uint32_t ct_acccur:4;
		}BIT;
	} CFG01;/*!< Offset: 0x11 (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t UFT0:5;
			volatile uint32_t GPADC1:1;
			volatile uint32_t UFT1:1;
			volatile uint32_t GPADC2:1;
			volatile uint32_t UFT2:1;
			volatile uint32_t GPADC3:1;
			volatile uint32_t RXBBTSTsig:1;
			volatile uint32_t RXBBTSTsigFreq:1;
			volatile uint32_t CLK40M_source:1;
			volatile uint32_t SYNC_source:1;
			volatile uint32_t UFT3:10;
			volatile uint32_t NC:8;
		}BIT;
	} CFG02;/*!< Offset: 0x12 (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t TX1PowerManual:3;
			volatile uint32_t TX2PowerManual:3;
			volatile uint32_t TX3PowerManual:3;
			volatile uint32_t TX4PowerManual:3;
			volatile uint32_t TX5PowerManual:3;
			volatile uint32_t TX6PowerManual:3;
			volatile uint32_t TX7PowerManual:3;
			volatile uint32_t TX8PowerManual:3;
			volatile uint32_t UFT0:8;
		}BIT;
	} CFG03;/*!< Offset: 0x13 (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t TX1PowerAdj:4;
			volatile uint32_t TX2PowerAdj:4;
			volatile uint32_t TX3PowerAdj:4;
			volatile uint32_t TX4PowerAdj:4;
			volatile uint32_t TX5PowerAdj:4;
			volatile uint32_t TX6PowerAdj:4;
			volatile uint32_t TX7PowerAdj:4;
			volatile uint32_t TX8PowerAdj:4;
		}BIT;
	} CFG04;/*!< Offset: 0x14 (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t Gainsta3:2;
			volatile uint32_t Gainsta2:2;
			volatile uint32_t Gainsta1:2;
			volatile uint32_t UFT0:2;
			volatile uint32_t HPsta2:2;
			volatile uint32_t HPsta1:2;
			volatile uint32_t UFT1:20;
		}BIT;
	} CFG05;/*!< Offset: 0x15 (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t UFT0:32;
		}BIT;
	} CFG06;/*!< Offset: 0x16 (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t UFT0:32;
		}BIT;
	} CFG07;/*!< Offset: 0x17 (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t UFT0:32;
		}BIT;
	} CFG08;/*!< Offset: 0x18 (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t UFT0:16;
			volatile uint32_t losel:10;
			volatile uint32_t UFT1:6;
		}BIT;
	} CFG09;/*!< Offset: 0x19 (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t UFT0:32;
		}BIT;
	} CFG10;/*!< Offset: 0x1A (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t UFT0:32;
		}BIT;
	} CFG11;/*!< Offset: 0x1B (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t UFT0:32;
		}BIT;
	} CFG12;/*!< Offset: 0x1C (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t UFT0:32;
		}BIT;
	} CFG13;/*!< Offset: 0x1D (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t UFT0:32;
		}BIT;
	} CFG14;/*!< Offset: 0x1E (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t UFT0:16;
			volatile uint32_t RX_Gain0:4;
			volatile uint32_t UFT1:12;
		}BIT;
	} CFG15;/*!< Offset: 0x1F (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t UFT0:32;
		}BIT;
	} CFG16;/*!< Offset: 0x20 (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t rx0_offset:4;
            volatile uint32_t rx1_offset:4;
            volatile uint32_t rx2_offset:4;
            volatile uint32_t rx3_offset:4;
            volatile uint32_t rx4_offset:4;
            volatile uint32_t rx5_offset:4;
            volatile uint32_t rx6_offset:4;
            volatile uint32_t rx7_offset:4;
		}BIT;
	} CFG17;/*!< Offset: 0x21 (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t UFT0:32;
		}BIT;
	} CFG18;/*!< Offset: 0x22 (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t UFT0:32;
		}BIT;
	} CFG19;/*!< Offset: 0x23 (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t UFT0:8;
			volatile uint32_t MIPIrate0:13;
			volatile uint32_t UFT1:3;
			volatile uint32_t MIPIrate1:5;
			volatile uint32_t UFT2:1;
			volatile uint32_t MIPIrate2:2;
		}BIT;
	} CFG20;/*!< Offset: 0x24 (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t UFT0:32;
		}BIT;
	} CFG21;/*!< Offset: 0x25 (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t mipidphy_cfg0_ch0:8;
			volatile uint32_t mipidphy_cfg0_ch1:8;
			volatile uint32_t mipidphy_cfg0_ch2:8;
			volatile uint32_t mipidphy_cfg0_ch3:8;
		}BIT;
	} CFG22;/*!< Offset: 0x26 (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t mipidphy_cfg0_ch4:8;
			volatile uint32_t mipidphy_cfg0_ch5:8;
			volatile uint32_t mipidphy_cfg0_ch6:8;
			volatile uint32_t mipidphy_cfg0_ch7:8;
		}BIT;
	} CFG23;/*!< Offset: 0x27 (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t mipidphy_cfg0_chck:8;
			volatile uint32_t mipidphy_cfg0_chck2:8;
			volatile uint32_t mipidphy_cfg0:16;
		}BIT;
	} CFG24;/*!< Offset: 0x28 (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t UFT0:32;
		}BIT;
	} CFG25;/*!< Offset: 0x29 (RW)*/
	volatile const  uint32_t RESERVED1[5];           /*!< Offset: 0x2A (RFU)*/
} RC8088_ANA_st;


/***************************************************/
/*-----------------------COMMON--------------------*/
/***************************************************/
typedef struct{
	union                                       /*!< Offset: 0x2F (RW)*/
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t dclk_div:3;
			volatile const uint32_t RFU0:1;
			volatile uint32_t adc_dmux:3;
			volatile uint32_t clk_out_mode:1;
			volatile const uint32_t RFU1:8;
			volatile uint32_t gpio_oe:7;
			volatile const uint32_t RFU2:1;
			volatile uint32_t gpio_sta:7;
			volatile const uint32_t RFU3:1;
		}BIT;
	} COMMON_CFG1;
} RC8088_COMMON_st;

/*COMMON CFG1*/
#define RC8088_DCLK_DIV_Pos                    (0)
#define RC8088_DCLK_DIV_Msk                    (0x07u << RC8088_DCLK_DIV_Pos)
#define RC8088_ADC_DMUX_Pos                    (4)
#define RC8088_ADC_DMUX_Msk                    (0x07u << RC8088_ADC_DMUX_Pos)
#define RC8088_CLK_OUT_MODE_Pos                (7)
#define RC8088_CLK_OUT_MODE_Msk                (0x01u << RC8088_CLK_OUT_MODE_Pos)
#define RC8088_GPIO_OE_Pos                     (16)
#define RC8088_GPIO_OE_Msk                     (0x7Fu << RC8088_GPIO_OE_Pos)
#define RC8088_GPIO_STA_Pos                    (24)
#define RC8088_GPIO_STA_Msk                    (0x7Fu << RC8088_GPIO_STA_Pos)


/***************************************************/
/*---------------------PREP------------------------*/
/***************************************************/
typedef struct{
	union                                         
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t samp_pt:16;
			volatile uint32_t samp_pt_fac:12;
			volatile uint32_t samp_pt_rsfb:4;
		}BIT;
	} PREP_CFG0;/*!< Offset: 0x30 (RW)*/
	union                                         
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t chirp_num:16;
			volatile uint32_t chirp_rma:4;
			volatile uint32_t pp_num:4;
			volatile uint32_t rx_num:3;
			volatile const uint32_t RFU:5;
		}BIT;
	} PREP_CFG1;/*!< Offset: 0x31 (RW)*/
	union                                         
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t adc_clk_mode:1;
			volatile uint32_t adc_dsize:2;
			volatile uint32_t adc_test_mode:1;
			volatile uint32_t adc_cat_mode:1;
			volatile uint32_t adc_lsb:3;
			volatile const uint32_t RFU0:16;
			volatile uint32_t down_fac:4;
			volatile uint32_t cic_sec:3;
			volatile const uint32_t RFU1:1;
		}BIT;
	} PREP_CFG2;/*!< Offset: 0x32 (RW)*/
	union                                         
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t rx_antseq0:3;
			volatile const uint32_t RFU0:1;
			volatile uint32_t rx_antseq1:3;
			volatile const uint32_t RFU1:1;
			volatile uint32_t rx_antseq2:3;
			volatile const uint32_t RFU2:1;
			volatile uint32_t rx_antseq3:3;
			volatile const uint32_t RFU3:1;
			volatile uint32_t rx_antseq4:3;
			volatile const uint32_t RFU4:1;
			volatile uint32_t rx_antseq5:3;
			volatile const uint32_t RFU5:1;
			volatile uint32_t rx_antseq6:3;
			volatile const uint32_t RFU6:1;
			volatile uint32_t rx_antseq7:3;
			volatile const uint32_t RFU7:1;			
		}BIT;
	} PREP_CFG3;/*!< Offset: 0x33 (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t cq2_timing_limit:15;
			volatile const uint32_t RFU0:1;
			volatile uint32_t cq1_pt_fac:6;
			volatile const uint32_t RFU1:2;
			volatile uint32_t cq1_pt_rsfb:3;
			volatile const uint32_t RFU2:5;
		}BIT;
	} PREP_CFG4;/*!< Offset: 0x34 (RW)*/
 	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t cq_sec_num:6;
			volatile const uint32_t RFU0:2;
			volatile uint32_t cq_pt_num:6;
			volatile const uint32_t RFU1:2;
			volatile uint32_t cq12_ch_num:3;
			volatile const uint32_t RFU2:13;
		}BIT;
	} PREP_CFG5;/*!< Offset: 0x35 (RW)*/
 	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t ramp_cnt:16;
			volatile const uint32_t RFU0:16;
		}BIT;
	} PREP_STA0;/*!< Offset: 0x36 (RW)*/
	volatile const  uint32_t RESERVED[5];                   /*!< Offset: 0x37 (RFU)*/
} RC8088_PREP_st;

/*PREP CFG0*/
#define RC8088_SAMP_PT_Pos                     (0)
#define RC8088_SAMP_PT_Msk                     (0xFFFFu << RC8088_SAMP_PT_Pos)
#define RC8088_SAMP_PT_FAC_Pos                 (16)
#define RC8088_SAMP_PT_FAC_Msk                 (0x0FFFu << RC8088_SAMP_PT_FAC_Pos)
#define RC8088_SAMP_PT_RSFB_Pos                (28)
#define RC8088_SAMP_PT_RSFB_Msk                (0x0Fu << RC8088_SAMP_PT_RSFB_Pos)

/*PREP CFG1*/
#define RC8088_CHIRP_NUM_Pos                   (0)
#define RC8088_CHIRP_NUM_Msk                   (0xFFFFu << RC8088_CHIRP_NUM_Pos)
#define RC8088_CHIRP_RMA_Pos                   (16)
#define RC8088_CHIRP_RMA_Msk                   (0x0Fu << RC8088_CHIRP_RMA_Pos)
#define RC8088_PP_NUM_Pos                      (20)
#define RC8088_PP_NUM_Msk                      (0x0Fu << RC8088_PP_NUM_Pos)
#define RC8088_RX_NUM_Pos                      (24)
#define RC8088_RX_NUM_Msk                      (0x07u << RC8088_RX_NUM_Pos)

/*PREP CFG2*/
#define RC8088_ADC_CLK_MODE_Pos                (0)
#define RC8088_ADC_CLK_MODE_Msk                (0x01u << RC8088_ADC_CLK_MODE_Pos)
#define RC8088_ADC_DSIZE_Pos                   (1)
#define RC8088_ADC_DSIZE_Msk                   (0x03u << RC8088_ADC_DSIZE_Pos)
#define RC8088_ADC_TEST_MODE_Pos               (3)
#define RC8088_ADC_TEST_MODE_Msk               (0x01u << RC8088_ADC_TEST_MODE_Pos)
#define RC8088_ADC_CAT_MODE_Pos                (4)
#define RC8088_ADC_CAT_MODE_Msk                (0x01u << RC8088_ADC_CAT_MODE_Pos)
#define RC8088_ADC_LSB_Pos                     (5)
#define RC8088_ADC_LSB_Msk                     (0x07u << RC8088_ADC_LSB_Pos)
#define RC8088_DOWN_FAC_Pos                    (24)
#define RC8088_DOWN_FAC_Msk                    (0x0Fu << RC8088_DOWN_FAC_Pos)
#define RC8088_CIC_SEC_Pos                     (28)
#define RC8088_CIC_SEC_Msk                     (0x07u << RC8088_CIC_SEC_Pos)

/*PREP CFG3*/
#define RC8088_RX_ANT_SEQ0_Pos                 (0)
#define RC8088_RX_ANT_SEQ0_Msk                 (0x07u << RC8088_RX_ANT_SEQ0_Pos)
#define RC8088_RX_ANT_SEQ1_Pos                 (4)
#define RC8088_RX_ANT_SEQ1_Msk                 (0x07u << RC8088_RX_ANT_SEQ1_Pos)
#define RC8088_RX_ANT_SEQ2_Pos                 (8)
#define RC8088_RX_ANT_SEQ2_Msk                 (0x07u << RC8088_RX_ANT_SEQ2_Pos)
#define RC8088_RX_ANT_SEQ3_Pos                 (12)
#define RC8088_RX_ANT_SEQ3_Msk                 (0x07u << RC8088_RX_ANT_SEQ3_Pos)
#define RC8088_RX_ANT_SEQ4_Pos                 (16)
#define RC8088_RX_ANT_SEQ4_Msk                 (0x07u << RC8088_RX_ANT_SEQ4_Pos)
#define RC8088_RX_ANT_SEQ5_Pos                 (20)
#define RC8088_RX_ANT_SEQ5_Msk                 (0x07u << RC8088_RX_ANT_SEQ5_Pos)
#define RC8088_RX_ANT_SEQ6_Pos                 (24)
#define RC8088_RX_ANT_SEQ6_Msk                 (0x07u << RC8088_RX_ANT_SEQ6_Pos)
#define RC8088_RX_ANT_SEQ7_Pos                 (28)
#define RC8088_RX_ANT_SEQ7_Msk                 (0x07u << RC8088_RX_ANT_SEQ7_Pos)

/*PREP CFG4*/
#define RC8088_CQ2_TIMING_LIMIT_Pos            (0)
#define RC8088_CQ2_TIMING_LIMIT_Msk            (0x7FFFu << RC8088_CQ2_TIMING_LIMIT_Pos)
#define RC8088_CQ1_PT_FAC_Pos                  (16)
#define RC8088_CQ1_PT_FAC_Msk                  (0x3Fu << RC8088_CQ1_PT_FAC_Pos)
#define RC8088_CQ1_PT_RSFB_Pos                 (24)
#define RC8088_CQ1_PT_RSFB_Msk                 (0x07u << RC8088_CQ1_PT_RSFB_Pos)

/*PREP CFG5*/
#define RC8088_CQ_SEC_NUM_Pos                  (0)
#define RC8088_CQ_SEC_NUM_Msk                  (0x3Fu << RC8088_CQ_SEC_NUM_Pos)
#define RC8088_CQ_PT_NUM_Pos                   (8)
#define RC8088_CQ_PT_NUM_Msk                   (0x3Fu << RC8088_CQ_PT_NUM_Pos)
#define RC8088_CQ12_CH_NUM_Pos                 (16)
#define RC8088_CQ12_CH_NUM_Msk                 (0x07u << RC8088_CQ12_CH_NUM_Pos)

/*PREP STA0*/
#define RC8088_RAMP_CNT_Pos                    (0)
#define RC8088_RAMP_CNT_Msk                    (0xFFFFu << RC8088_RAMP_CNT_Pos)


/***************************************************/
/*---------------------P10 CFG---------------------*/
/***************************************************/
typedef struct{
 	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t zo_zero_len:2;
			volatile uint32_t zo_mode:2;
			volatile uint32_t zo_diff_mode:2;
			volatile uint32_t dc_removal:1;
			volatile const uint32_t RFU0:1;
			volatile uint32_t diff_mul_fac:4;
			volatile uint32_t timing_mul_fac:4;
			volatile uint32_t valid_ch_num:2;
			volatile const uint32_t RFU1:10;
			volatile uint32_t sw_diff_mode:1;
			volatile uint32_t sw_timing_mode:1;
			volatile const uint32_t RFU2:2;
		}BIT;
	} P10_CFG0;/*!< Offset: 0x3C (RW)*/
 	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t sw_diff_thres:15;
			volatile const uint32_t RFU0:1;
			volatile uint32_t sw_timing_thres:15;
			volatile const uint32_t RFU1:1;
		}BIT;
	} P10_CFG1;/*!< Offset: 0x3D (RW)*/
	volatile const  uint32_t RESERVED[2];                   /*!< Offset: 0x3E (RFU)*/
} RC8088_P10_st;

/*P10 CFG0*/
#define RC8088_ZO_ZERO_LEN_Pos                 (0)
#define RC8088_ZO_ZERO_LEN_Msk                 (0x03u << RC8088_ZO_ZERO_LEN_Pos)
#define RC8088_ZO_MODE_Pos                     (2)
#define RC8088_ZO_MODE_Msk                     (0x03u << RC8088_ZO_MODE_Pos)
#define RC8088_ZO_DIFF_MODE_Pos                (4)
#define RC8088_ZO_DIFF_MODE_Msk                (0x03u << RC8088_ZO_DIFF_MODE_Pos)
#define RC8088_DC_REMOVAL_Pos                  (6)
#define RC8088_DC_REMOVAL_Msk                  (0x01u << RC8088_DC_REMOVAL_Pos)
#define RC8088_DIFF_MUL_FAC_Pos                (8)
#define RC8088_DIFF_MUL_FAC_Msk                (0x0Fu << RC8088_DIFF_MUL_FAC_Pos)
#define RC8088_TIMING_MUL_FAC_Pos              (12)
#define RC8088_TIMING_MUL_FAC_Msk              (0x0Fu << RC8088_TIMING_MUL_FAC_Pos)
#define RC8088_VALID_CH_NUM_Pos                (16)
#define RC8088_VALID_CH_NUM_Msk                (0x03u << RC8088_VALID_CH_NUM_Pos)
#define RC8088_SW_DIFF_MODE_Pos                (28)
#define RC8088_SW_DIFF_MODE_Msk                (0x01u << RC8088_SW_DIFF_MODE_Pos)
#define RC8088_SW_TIMING_MODE_Pos              (29)
#define RC8088_SW_TIMING_MODE_Msk              (0x01u << RC8088_SW_TIMING_MODE_Pos)
/*P10 CFG1*/
#define RC8088_SW_DIFF_THRES_Pos               (0)
#define RC8088_SW_DIFF_THRES_Msk               (0x7FFFu << RC8088_SW_DIFF_THRES_Pos)
#define RC8088_SW_TIMING_THRES_Pos             (16)
#define RC8088_SW_TIMING_THRES_Msk             (0x7FFFu << RC8088_SW_TIMING_THRES_Pos)


/***************************************************/
/*---------------------DMA CFG---------------------*/
/***************************************************/
typedef struct{
 	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t entry_a_en:1;
			volatile uint32_t entry_b_en:1;
			volatile uint32_t entry_c_en:1;
			volatile uint32_t entry_d_en:1;
			volatile uint32_t entry_e_en:1;
			volatile const uint32_t RFU0:3;
			volatile uint32_t wr2mipi_dly:4;
			volatile uint32_t prep2rd_dly:4;
			volatile uint32_t burst_len:8;
			volatile uint32_t interCnt:1;
			volatile const uint32_t RFU1:3;
			volatile uint32_t trans_mode:1;
			volatile const uint32_t RFU2:3;
		}BIT;
	} DMA_CFG0;/*!< Offset: 0x40 (RW)*/
 	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t b_intraCnt:12;
			volatile uint32_t c_intraCnt:3;
			volatile const uint32_t RFU0:1;
			volatile uint32_t d_intraCnt:6;
			volatile const uint32_t RFU1:6;
			volatile uint32_t d_ch_num:2;
			volatile const uint32_t RFU2:2;
		}BIT;
	} DMA_CFG1;/*!< Offset: 0x41 (RW)*/
 	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t e_intraCnt:12;
			volatile const uint32_t RFU:20;
		}BIT;
	} DMA_CFG2;/*!< Offset: 0x42 (RW)*/
 	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t e_baseAddr:16;
			volatile uint32_t e_jumpCnt:1;
			volatile const uint32_t RFU:15;
		}BIT;
	} DMA_CFG3;/*!< Offset: 0x43 (RW)*/
	volatile const  uint32_t RESERVED[4];                   /*!< Offset: 0x44 (RFU)*/
} RC8088_DMA_st;

/*DMA CFG0*/
#define RC8088_ENTRY_A_EN_Pos                  (0)
#define RC8088_ENTRY_A_EN_Msk                  (0x01u << RC8088_ENTRY_A_EN_Pos)
#define RC8088_ENTRY_B_EN_Pos                  (1)
#define RC8088_ENTRY_B_EN_Msk                  (0x01u << RC8088_ENTRY_B_EN_Pos)
#define RC8088_ENTRY_C_EN_Pos                  (2)
#define RC8088_ENTRY_C_EN_Msk                  (0x01u << RC8088_ENTRY_C_EN_Pos)
#define RC8088_ENTRY_D_EN_Pos                  (3)
#define RC8088_ENTRY_D_EN_Msk                  (0x01u << RC8088_ENTRY_D_EN_Pos)
#define RC8088_ENTRY_E_EN_Pos                  (4)
#define RC8088_ENTRY_E_EN_Msk                  (0x01u << RC8088_ENTRY_E_EN_Pos)
#define RC8088_WR2MIPI_DLY_Pos                 (8)
#define RC8088_WR2MIPI_DLY_Msk                 (0x0Fu << RC8088_WR2MIPI_DLY_Pos)
#define RC8088_PREP2RD_DLY_Pos                 (12)
#define RC8088_PREP2RD_DLY_Msk                 (0x0Fu << RC8088_PREP2RD_DLY_Pos)
#define RC8088_BURST_LEN_Pos                   (16)
#define RC8088_BURST_LEN_Msk                   (0xFFu << RC8088_BURST_LEN_Pos)
#define RC8088_INTER_CNT_Pos                   (24)
#define RC8088_INTER_CNT_Msk                   (0x01u << RC8088_INTER_CNT_Pos)
#define RC8088_TRANS_MODE_Pos                  (28)
#define RC8088_TRANS_MODE_Msk                  (0x01u << RC8088_TRANS_MODE_Pos)
/*DMA CFG1*/
#define RC8088_B_INTRACNT_Pos                  (0)
#define RC8088_B_INTRACNT_Msk                  (0x0FFFu << RC8088_B_INTRACNT_Pos)
#define RC8088_C_INTRACNT_Pos                  (12)
#define RC8088_C_INTRACNT_Msk                  (0x07u << RC8088_C_INTRACNT_Pos)
#define RC8088_D_INTRACNT_Pos                  (16)
#define RC8088_D_INTRACNT_Msk                  (0x3Fu << RC8088_D_INTRACNT_Pos)
#define RC8088_D_CH_NUM_Pos                    (28)
#define RC8088_D_CH_NUM_Msk                    (0x03u << RC8088_D_CH_NUM_Pos)
/*DMA CFG2*/
#define RC8088_E_INTRACNT_Pos                  (0)
#define RC8088_E_INTRACNT_Msk                  (0x0FFFu << RC8088_E_INTRACNT_Pos)
/*DMA CFG3*/
#define RC8088_E_BASEADDR_Pos                  (0)
#define RC8088_E_BASEADDR_Msk                  (0xFFFFu << RC8088_E_BASEADDR_Pos)
#define RC8088_E_JUMPINC_Pos                   (16)
#define RC8088_E_JUMPINC_Msk                   (0x01u << RC8088_E_JUMPINC_Pos)


/***************************************************/
/*---------------------FFT CFG---------------------*/
/***************************************************/
typedef struct{
 	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t mode:1;
			volatile const uint32_t RFU0:3;
			volatile uint32_t fftPt:4;
			volatile const uint32_t RFU1:12;
			volatile uint32_t out_exp:4;
			volatile uint32_t out_mode:1;
			volatile const uint32_t RFU2:3;
			volatile uint32_t win_en:1;
			volatile uint32_t win_sym:1;
			volatile const uint32_t RFU3:2;
		}BIT;
	} FFT_CFG0;/*!< Offset: 0x48 (RW)*/
 	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t winLsfb:4;
			volatile const uint32_t RFU0:4;
			volatile uint32_t outSfb:4;
			volatile uint32_t outLsfEn:1;
			volatile const uint32_t RFU2:19;
		}BIT;
	} FFT_CFG1;/*!< Offset: 0x49 (RW)*/
 	union
	{
		volatile const uint32_t WORD;
		struct
		{
			volatile const uint32_t sesr_fft_pre_sft_ovf:1;
			volatile const uint32_t sesr_fft_bf_f2_ovf:1;
			volatile const uint32_t sesr_fft_bf_f3_ovf:1;
			volatile const uint32_t sesr_fft_tw_ovf:1;
			volatile const uint32_t sesr_fft_post_sft_ovf:1;
			volatile const uint32_t RFU0:27;
		}BIT;
	} FFT_STA0;/*!< Offset: 0x4A (RW)*/
	volatile const uint32_t RESERVED[5];                   /*!< Offset: 0x4B (RFU)*/
} RC8088_FFT_st;

/*FFT CFG0*/
#define RC8088_MODE_Pos                        (0)
#define RC8088_MODE_Msk                        (0x01u << RC8088_MODE_Pos)
#define RC8088_FFT_PT_Pos                      (4)
#define RC8088_FFT_PT_Msk                      (0x0Fu << RC8088_FFT_PT_Pos)
#define RC8088_OUT_EXP_Pos                     (20)
#define RC8088_OUT_EXP_Msk                     (0x0Fu << RC8088_OUT_EXP_Pos)
#define RC8088_OUT_MODE_Pos                    (24)
#define RC8088_OUT_MODE_Msk                    (0x01u << RC8088_OUT_MODE_Pos)
#define RC8088_WIN_EN_Pos                      (28)
#define RC8088_WIN_EN_Msk                      (0x01u << RC8088_WIN_EN_Pos)
#define RC8088_WIN_SYM_Pos                     (29)
#define RC8088_WIN_SYM_Msk                     (0x01u << RC8088_WIN_SYM_Pos)
/*FFT CFG1*/
#define RC8088_WIN_LSFB_Pos                    (0)
#define RC8088_WIN_LSFB_Msk                    (0x0Fu << RC8088_WIN_LSFB_Pos)
#define RC8088_OUT_SFB_Pos                     (8)
#define RC8088_OUT_SFB_Msk                     (0x0Fu << RC8088_OUT_SFB_Pos)
#define RC8088_OUT_LSF_EN_Pos                  (12)
#define RC8088_OUT_LSF_EN_Msk                  (0x01u << RC8088_OUT_LSF_EN_Pos)
/*FFT STA0*/
#define RC8088_SESR_FFT_PRE_SFT_OVF_Pos        (0)
#define RC8088_SESR_FFT_PRE_SFT_OVF_Msk        (0x01u << RC8088_SESR_FFT_PRE_SFT_OVF_Pos)
#define RC8088_SESR_FFT_BF_F2_OVF_Pos          (1)
#define RC8088_SESR_FFT_BF_F2_OVF_Msk          (0x01u << RC8088_SESR_FFT_BF_F2_OVF_Pos)
#define RC8088_SESR_FFT_BF_F3_OVF_Pos          (2)
#define RC8088_SESR_FFT_BF_F3_OVF_Msk          (0x01u << RC8088_SESR_FFT_BF_F3_OVF_Pos)
#define RC8088_SESR_FFT_TW_OVF_Pos             (3)
#define RC8088_SESR_FFT_TW_OVF_Msk             (0x01u << RC8088_SESR_FFT_TW_OVF_Pos)
#define RC8088_SESR_FFT_POST_SFT_OVF_Pos       (4)
#define RC8088_SESR_FFT_POST_SFT_OVF_Msk       (0x01u << RC8088_SESR_FFT_POST_SFT_OVF_Pos)


/***************************************************/
/*---------------------MIPI CFG--------------------*/
/***************************************************/
typedef struct{
 	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t mipi_wlevel:10;
			volatile const uint32_t RFU0:2;
			volatile uint32_t mipi_data_type:2;
			volatile const uint32_t RFU1:2;
			volatile uint32_t mipi_dlane_mode:2;
			volatile const uint32_t RFU2:2;
			volatile uint32_t mipi0_en:1;
			volatile uint32_t mipi1_en:1;
			volatile uint32_t mipi_64bit_mode:1;
			volatile uint32_t mipi_crc_en:1;
			volatile const uint32_t RFU3:8;
		}BIT;
	} MIPI_CFG0;/*!< Offset: 0x50 (RW)*/
 	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t mipi_payload_len:16;
			volatile uint32_t mipi_chirp_num:16;
		}BIT;
	} MIPI_CFG1;/*!< Offset: 0x51 (RW)*/
 	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t mipi_sf_head:8;
			volatile uint32_t mipi_head_cfg_en:1;
			volatile const uint32_t RFU:23;
		}BIT;
	} MIPI_CFG2;/*!< Offset: 0x52 (RW)*/
 	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t mipi_lp_head:8;
			volatile uint32_t mipi_el_head:8;
			volatile uint32_t mipi_sl_head:8;
			volatile uint32_t mipi_ef_head:8;
		}BIT;
	} MIPI_CFG3;/*!< Offset: 0x53 (RW)*/
 	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t mipi_ths_trail:4;
			volatile uint32_t mipi_ths_zero:4;
			volatile uint32_t mipi_tlpx:4;
			volatile uint32_t mipi_tck_trail:4;
			volatile uint32_t mipi_tck_post:4;
			volatile uint32_t mipi_tck_zero:4;
			volatile uint32_t mipi_tck_pre:4;
		}BIT;
	} MIPI_CFG4;/*!< Offset: 0x54 (RW)*/
	volatile const  uint32_t RESERVED0[3];                  /*!< Offset: 0x55 (RFU)*/
 	union
	{
		volatile const uint32_t WORD;
		struct
		{
			volatile const uint32_t mipi_dl0_sta:4;
			volatile const uint32_t mipi_cl0_sta:2;
			volatile const uint32_t RFU0:2;
			volatile const uint32_t mipi_hs0_sta:3;
			volatile const uint32_t RFU1:1;
			volatile const uint32_t mipi_lp0_sta:2;
			volatile const uint32_t RFU2:2;
			volatile const uint32_t mipi_dl1_sta:4;
			volatile const uint32_t mipi_cl1_sta:2;
			volatile const uint32_t RFU3:2;
			volatile const uint32_t mipi_hs1_sta:3;
			volatile const uint32_t RFU4:1;
			volatile const uint32_t mipi_lp1_sta:2;
			volatile const uint32_t RFU5:1;
			volatile const uint32_t mipi_lp_end:1;
		}BIT;
	} MIPI_STA0;/*!< Offset: 0x58 (RW)*/
	 	union
	{
		volatile const uint32_t WORD;
		struct
		{
			volatile const uint32_t mipi_afifo_len:8;
			volatile const uint32_t RFU:24;

		}BIT;
	} MIPI_STA1;/*!< Offset: 0x59 (RW)*/
	volatile const  uint32_t RESERVED1[6];                  /*!< Offset: 0x5A (RFU)*/
} RC8088_MIPI_st;

/*MIPI CFG0*/
#define RC8088_MIPI_WLEVEL_Pos                 (0)
#define RC8088_MIPI_WLEVEL_Msk                 (0x03FFu << RC8088_MIPI_WLEVEL_Pos)
#define RC8088_MIPI_DATA_TYPE_Pos              (12)
#define RC8088_MIPI_DATA_TYPE_Msk              (0x03u << RC8088_MIPI_DATA_TYPE_Pos)
#define RC8088_MIPI_DLANE_MODE_Pos             (16)
#define RC8088_MIPI_DLANE_MODE_Msk             (0x03u << RC8088_MIPI_DLANE_MODE_Pos)
#define RC8088_MIPI0_EN_Pos                    (20)
#define RC8088_MIPI0_EN_Msk                    (0x01u << RC8088_MIPI0_EN_Pos)
#define RC8088_MIPI1_EN_Pos                    (21)
#define RC8088_MIPI1_EN_Msk                    (0x01u << RC8088_MIPI1_EN_Pos)
#define RC8088_MIPI_64BIT_MODE_Pos             (22)
#define RC8088_MIPI_64BIT_MODE_Msk             (0x01u << RC8088_MIPI_64BIT_MODE_Pos)
#define RC8088_MIPI_CRC_EN_Pos                 (23)
#define RC8088_MIPI_CRC_EN_Msk                 (0x01u << RC8088_MIPI_CRC_EN_Pos)

/*MIPI CFG1*/
#define RC8088_MIPI_PAYLOAD_LEN_Pos            (0)
#define RC8088_MIPI_PAYLOAD_LEN_Msk            (0xFFFFu << RC8088_MIPI_PAYLOAD_LEN_Pos)
#define RC8088_MIPI_CHIRP_NUM_Pos              (16)
#define RC8088_MIPI_CHIRP_NUM_Msk              (0xFFFFu << RC8088_MIPI_CHIRP_NUM_Pos)

/*MIPI CFG2*/
#define RC8088_MIPI_SF_HEAD_Pos                (0)
#define RC8088_MIPI_SF_HEAD_Msk                (0xFFu << RC8088_MIPI_SF_HEAD_Pos)
#define RC8088_MIPI_HEAD_CFG_EN_Pos            (8)
#define RC8088_MIPI_HEAD_CFG_EN_Msk            (0x01u << RC8088_MIPI_HEAD_CFG_EN_Pos)

/*MIPI CFG3*/
#define RC8088_MIPI_LP_HEAD_Pos                (0)
#define RC8088_MIPI_LP_HEAD_Msk                (0xFFu << RC8088_MIPI_LP_HEAD_Pos)
#define RC8088_MIPI_EL_HEAD_Pos                (8)
#define RC8088_MIPI_EL_HEAD_Msk                (0xFFu << RC8088_MIPI_EL_HEAD_Pos)
#define RC8088_MIPI_SL_HEAD_Pos                (16)
#define RC8088_MIPI_SL_HEAD_Msk                (0xFFu << RC8088_MIPI_SL_HEAD_Pos)
#define RC8088_MIPI_EF_HEAD_Pos                (24)
#define RC8088_MIPI_EF_HEAD_Msk                (0xFFu << RC8088_MIPI_EF_HEAD_Pos)

/*MIPI CFG4*/
#define RC8088_MIPI_THS_TRAIL_Pos              (0)
#define RC8088_MIPI_THS_TRAIL_Msk              (0x0Fu << RC8088_MIPI_THS_TRAIL_Pos)
#define RC8088_MIPI_THS_ZERO_Pos               (4)
#define RC8088_MIPI_THS_ZERO_Msk               (0x0Fu << RC8088_MIPI_THS_ZERO_Pos)
#define RC8088_MIPI_TLPX_Pos                   (8)
#define RC8088_MIPI_TLPX_Msk                   (0x0Fu << RC8088_MIPI_TLPX_Pos)
#define RC8088_MIPI_TCK_TRAIL_Pos              (12)
#define RC8088_MIPI_TCK_TRAIL_Msk              (0x0Fu << RC8088_MIPI_TCK_TRAIL_Pos)
#define RC8088_MIPI_TCK_POST_Pos               (16)
#define RC8088_MIPI_TCK_POST_Msk               (0x0Fu << RC8088_MIPI_TCK_POST_Pos)
#define RC8088_MIPI_TCK_ZERO_Pos               (20)
#define RC8088_MIPI_TCK_ZERO_Msk               (0x0Fu << RC8088_MIPI_TCK_ZERO_Pos)
#define RC8088_MIPI_TCK_PRE_Pos                (24)
#define RC8088_MIPI_TCK_PRE_Msk                (0x0Fu << RC8088_MIPI_TCK_PRE_Pos)

/*MIPI STA0*/
#define RC8088_MIPI_DL0_STA_Pos                (0)
#define RC8088_MIPI_DL0_STA_Msk                (0x0Fu << RC8088_MIPI_DL0_STA_Pos)
#define RC8088_MIPI_CL0_STA_Pos                (4)
#define RC8088_MIPI_CL0_STA_Msk                (0x03u << RC8088_MIPI_CL0_STA_Pos)
#define RC8088_MIPI_HS0_STA_Pos                (8)
#define RC8088_MIPI_HS0_STA_Msk                (0x07u << RC8088_MIPI_HS0_STA_Pos)
#define RC8088_MIPI_LP0_STA_Pos                (12)
#define RC8088_MIPI_LP0_STA_Msk                (0x03u << RC8088_MIPI_LP0_STA_Pos)
#define RC8088_MIPI_DL1_STA_Pos                (16)
#define RC8088_MIPI_DL1_STA_Msk                (0x0Fu << RC8088_MIPI_DL1_STA_Pos)
#define RC8088_MIPI_CL1_STA_Pos                (20)
#define RC8088_MIPI_CL1_STA_Msk                (0x03u << RC8088_MIPI_CL1_STA_Pos)
#define RC8088_MIPI_HS1_STA_Pos                (24)
#define RC8088_MIPI_HS1_STA_Msk                (0x07u << RC8088_MIPI_HS1_STA_Pos)
#define RC8088_MIPI_LP1_STA_Pos                (28)
#define RC8088_MIPI_LP1_STA_Msk                (0x03u << RC8088_MIPI_LP1_STA_Pos)
#define RC8088_MIPI_LP_END_Pos                 (31)
#define RC8088_MIPI_LP_END_Msk                 (0x01u << RC8088_MIPI_LP_END_Pos)

/*MIPI STA1*/
#define RC8088_MIPI_AFIFO_LEN_Pos              (0)
#define RC8088_MIPI_AFIFO_LEN_Msk              (0xFFu << RC8088_MIPI_AFIFO_LEN_Pos)


/***************************************************/
/*-----------------------INT-----------------------*/
/***************************************************/
typedef struct{
 	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile const uint32_t RFU0:1;
			volatile uint32_t prep_ramp_end:1;
			volatile const uint32_t RFU1:1;
			volatile uint32_t prep_frame_end:1;
			volatile uint32_t ramp_pedge:1;
			volatile uint32_t ramp_nedge:1;
			volatile uint32_t dma_intra_end:1;
			volatile uint32_t dma_inter_end:1;
			volatile uint32_t fft_calc_last2_end:1;
			volatile uint32_t fft_calc_end:1;
			volatile uint32_t fft_output_end:1;
			volatile const uint32_t RFU2:13;
			volatile uint32_t reg_crc_end:1;
			volatile uint32_t clr_mem_end:1;
			volatile const uint32_t RFU3:6;
		}BIT;
	} IMR;/*!< Offset: 0x60 (RW)*/
 	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t zo0_thres_excess:1;
			volatile uint32_t zo1_thres_excess:1;
			volatile uint32_t zo2_thres_excess:1;
			volatile uint32_t zo3_thres_excess:1;
			volatile uint32_t fft_calc_ovf:1;
			volatile uint32_t fft_pre_ovf:1;
			volatile uint32_t fft_post_ovf:1;
			volatile const uint32_t RFU0:1;
			volatile uint32_t reg_crc_err:1;
			volatile uint32_t spi_crc_err:1;
			volatile uint32_t mipi_ff_udf:1;
			volatile uint32_t mipi_ff_ovf:1;
			volatile uint32_t txpbuf_crash:1;
			volatile uint32_t cbuf_crash:1;
			volatile uint32_t wbuf_crash:1;
			volatile uint32_t fbuf_crash:1;
			volatile uint32_t dbuf_crash:1;
			volatile uint32_t pbuf_crash:1;
			volatile uint32_t ibuf_crash:1;
			volatile uint32_t invalid_addr:1;
			volatile uint32_t txpbuf_ecc_err:1;
			volatile uint32_t cbuf_ecc_err:1;
			volatile uint32_t wbuf_ecc_err:1;
			volatile uint32_t fbuf_ecc_err:1;
			volatile uint32_t dbuf_ecc_err:1;
			volatile uint32_t pbuf_ecc_err:1;
			volatile uint32_t ibuf_ecc_err:1;
			volatile uint32_t RFU1:5;
		}BIT;
	} EMR0;/*!< Offset: 0x61 (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t EMR1:32;
		}BIT;
	} EMR1;/*!< Offset: 0x62 (RW)*/
 	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile const uint32_t esr:1;
			volatile uint32_t prep_ramp_end:1;
			volatile const uint32_t RFU1:1;
			volatile uint32_t prep_frame_end:1;
			volatile uint32_t ramp_pedge:1;
			volatile uint32_t ramp_nedge:1;
			volatile uint32_t dma_intra_end:1;
			volatile uint32_t dma_inter_end:1;
			volatile uint32_t fft_calc_last2_end:1;
			volatile uint32_t fft_calc_end:1;
			volatile uint32_t fft_output_end:1;
			volatile const uint32_t RFU2:13;
			volatile uint32_t reg_crc_end:1;
			volatile uint32_t clr_mem_end:1;
			volatile const uint32_t RFU3:6;
		}BIT;
	} ISR;/*!< Offset: 0x63 (RO-WC)*/
 	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t zo0_thres_excess:1;
			volatile uint32_t zo1_thres_excess:1;
			volatile uint32_t zo2_thres_excess:1;
			volatile uint32_t zo3_thres_excess:1;
			volatile uint32_t fft_calc_ovf:1;
			volatile uint32_t fft_pre_ovf:1;
			volatile uint32_t fft_post_ovf:1;
			volatile const uint32_t RFU0:1;
			volatile uint32_t reg_crc_err:1;
			volatile uint32_t spi_crc_err:1;
			volatile uint32_t mipi_ff_udf:1;
			volatile uint32_t mipi_ff_ovf:1;
			volatile uint32_t txpbuf_crash:1;
			volatile uint32_t cbuf_crash:1;
			volatile uint32_t wbuf_crash:1;
			volatile uint32_t fbuf_crash:1;
			volatile uint32_t dbuf_crash:1;
			volatile uint32_t pbuf_crash:1;
			volatile uint32_t ibuf_crash:1;
			volatile uint32_t invalid_addr:1;
			volatile uint32_t txpbuf_ecc_err:1;
			volatile uint32_t cbuf_ecc_err:1;
			volatile uint32_t wbuf_ecc_err:1;
			volatile uint32_t fbuf_ecc_err:1;
			volatile uint32_t dbuf_ecc_err:1;
			volatile uint32_t pbuf_ecc_err:1;
			volatile uint32_t ibuf_ecc_err:1;
			volatile const uint32_t RFU1:5;
		}BIT;
	} ESR0;/*!< Offset: 0x64 (RO-WC)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t ESR1:32;
		}BIT;
	} ESR1;/*!< Offset: 0x65 (RO-WC)*/
	volatile const  uint32_t RESERVED[10];                  /*!< Offset: 0x66 (RFU)*/
} RC8088_INT_st;

/*IMR*/
#define RC8088_PREP_RAMP_END_Pos               (1)
#define RC8088_PREP_RAMP_END_Msk               (0x01u << RC8088_PREP_RAMP_END_Pos)
#define RC8088_PREP_FRAME_END_Pos              (3)
#define RC8088_PREP_FRAME_END_Msk              (0x01u << RC8088_PREP_FRAME_END_Pos)
#define RC8088_PREP_PEDGE_Pos                  (4)
#define RC8088_PREP_PEDGE_Msk                  (0x01u << RC8088_PREP_PEDGE_Pos)
#define RC8088_PREP_NEDGE_Pos                  (5)
#define RC8088_PREP_NEDGE_Msk                  (0x01u << RC8088_PREP_NEDGE_Pos)
#define RC8088_DMA_INTRA_END_Pos               (6)
#define RC8088_DMA_INTRA_END_Msk               (0x01u << RC8088_DMA_INTRA_END_Pos)
#define RC8088_DMA_INTER_END_Pos               (7)
#define RC8088_DMA_INTER_END_Msk               (0x01u << RC8088_DMA_INTER_END_Pos)
#define RC8088_FFT_CALC_LAST2_END_Pos          (8)
#define RC8088_FFT_CALC_LAST2_END_Msk          (0x01u << RC8088_FFT_CALC_LAST2_END_Pos)
#define RC8088_FFT_CALC_END_Pos                (9)
#define RC8088_FFT_CALC_END_Msk                (0x01u << RC8088_FFT_CALC_END_Pos)
#define RC8088_FFT_OUTPUT_END_Pos              (10)
#define RC8088_FFT_OUTPUT_END_Msk              (0x01u << RC8088_FFT_OUTPUT_END_Pos)
#define RC8088_REG_CRC_END_Pos                 (24)
#define RC8088_REG_CRC_END_Msk                 (0x01u << RC8088_REG_CRC_END_Pos)
#define RC8088_CLR_MEM_END_Pos                 (25)
#define RC8088_CLR_MEM_END_Msk                 (0x01u << RC8088_CLR_MEM_END_Pos)

/*EMR0*/
#define RC8088_ZO0_THRES_EXCESS_Pos            (0)
#define RC8088_ZO0_THRES_EXCESS_Msk            (0x01u << RC8088_ZO0_THRES_EXCESS_Pos)
#define RC8088_ZO1_THRES_EXCESS_Pos            (1)
#define RC8088_ZO1_THRES_EXCESS_Msk            (0x01u << RC8088_ZO1_THRES_EXCESS_Pos)
#define RC8088_ZO2_THRES_EXCESS_Pos            (2)
#define RC8088_ZO2_THRES_EXCESS_Msk            (0x01u << RC8088_ZO2_THRES_EXCESS_Pos)
#define RC8088_ZO3_THRES_EXCESS_Pos            (3)
#define RC8088_ZO3_THRES_EXCESS_Msk            (0x01u << RC8088_ZO3_THRES_EXCESS_Pos)
#define RC8088_FFT_CALC_OVF_Pos                (4)
#define RC8088_FFT_CALC_OVF_Msk                (0x01u << RC8088_FFT_CALC_OVF_Pos)
#define RC8088_FFT_PRE_OVF_Pos                 (5)
#define RC8088_FFT_PRE_OVF_Msk                 (0x01u << RC8088_FFT_PRE_OVF_Pos)
#define RC8088_FFT_POST_OVF_Pos                (6)
#define RC8088_FFT_POST_OVF_Msk                (0x01u << RC8088_FFT_POST_OVF_Pos)
#define RC8088_REG_CRC_ERR_Pos                 (8)
#define RC8088_REG_CRC_ERR_Msk                 (0x01u << RC8088_REG_CRC_ERR_Pos)
#define RC8088_SPI_CRC_ERR_Pos                 (9)
#define RC8088_SPI_CRC_ERR_Msk                 (0x01u << RC8088_SPI_CRC_ERR_Pos)
#define RC8088_MIPI_FF_UDF_Pos                 (10)
#define RC8088_MIPI_FF_UDF_Msk                 (0x01u << RC8088_MIPI_FF_UDF_Pos)
#define RC8088_MIPI_FF_OVF_Pos                 (11)
#define RC8088_MIPI_FF_OVF_Msk                 (0x01u << RC8088_MIPI_FF_OVF_Pos)
#define RC8088_TXPBUF_CRASH_Pos                (12)
#define RC8088_TXPBUF_CRASH_Msk                (0x01u << RC8088_TXPBUF_CRASH_Pos)
#define RC8088_CBUF_CRASH_Pos                  (13)
#define RC8088_CBUF_CRASH_Msk                  (0x01u << RC8088_CBUF_CRASH_Pos)
#define RC8088_WBUF_CRASH_Pos                  (14)
#define RC8088_WBUF_CRASH_Msk                  (0x01u << RC8088_WBUF_CRASH_Pos)
#define RC8088_FBUF_CRASH_Pos                  (15)
#define RC8088_FBUF_CRASH_Msk                  (0x01u << RC8088_FBUF_CRASH_Pos)
#define RC8088_DBUF_CRASH_Pos                  (16)
#define RC8088_DBUF_CRASH_Msk                  (0x01u << RC8088_DBUF_CRASH_Pos)
#define RC8088_PBUF_CRASH_Pos                  (17)
#define RC8088_PBUF_CRASH_Msk                  (0x01u << RC8088_PBUF_CRASH_Pos)
#define RC8088_IBUF_CRASH_Pos                  (18)
#define RC8088_IBUF_CRASH_Msk                  (0x01u << RC8088_IBUF_CRASH_Pos)
#define RC8088_INVALID_ADDR_Pos                (19)
#define RC8088_INVALID_ADDR_Msk                (0x01u << RC8088_INVALID_ADDR_Pos)
#define RC8088_TXPBUF_ECC_ERR_Pos              (20)
#define RC8088_TXPBUF_ECC_ERR_Msk              (0x01u << RC8088_TXPBUF_ECC_ERR_Pos)
#define RC8088_CBUF_ECC_ERR_Pos                (21)
#define RC8088_CBUF_ECC_ERR_Msk                (0x01u << RC8088_CBUF_ECC_ERR_Pos)
#define RC8088_WBUF_ECC_ERR_Pos                (22)
#define RC8088_WBUF_ECC_ERR_Msk                (0x01u << RC8088_WBUF_ECC_ERR_Pos)
#define RC8088_FBUF_ECC_ERR_Pos                (23)
#define RC8088_FBUF_ECC_ERR_Msk                (0x01u << RC8088_FBUF_ECC_ERR_Pos)
#define RC8088_DBUF_ECC_ERR_Pos                (24)
#define RC8088_DBUF_ECC_ERR_Msk                (0x01u << RC8088_DBUF_ECC_ERR_Pos)
#define RC8088_PBUF_ECC_ERR_Pos                (25)
#define RC8088_PBUF_ECC_ERR_Msk                (0x01u << RC8088_PBUF_ECC_ERR_Pos)
#define RC8088_IBUF_ECC_ERR_Pos                (26)
#define RC8088_IBUF_ECC_ERR_Msk                (0x01u << RC8088_IBUF_ECC_ERR_Pos)

/*EMR1*/
#define RC8088_ANALOG_ERROR_Pos                (0)
#define RC8088_ANALOG_ERROR_Msk                (0xFFFFFFFFu << RC8088_ANALOG_ERROR_Pos)

/*ISR*/
#define RC8088_ESR_Pos                         (0)
#define RC8088_ESR_Msk                         (0x01u << RC8088_ESR_Pos)


/***************************************************/
/*-----------------------OP GATE-------------------*/
/***************************************************/
typedef struct{
 	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t gate_prep:1;
			volatile uint32_t gate_tstat:1;
			volatile uint32_t gate_fft0:1;
			volatile uint32_t gate_fft1:1;
			volatile uint32_t gate_edma:1;
			volatile uint32_t gate_mipi:1;
			volatile uint32_t gate_wgen:1;
			volatile const uint32_t RFU:25;
		}BIT;
	} OP_GATE;/*!< Offset: 0x70 (RW)*/
	volatile const  uint32_t RESERVED[7];                   /*!< Offset: 0x71 (RFU)*/
} RC8088_OpGate_st;

/*OP_GATE*/
#define RC8088_GATE_PREP_Pos                   (0)
#define RC8088_GATE_PREP_Msk                   (0x01u << RC8088_GATE_PREP_Pos)
#define RC8088_GATE_TSTAT_Pos                  (1)
#define RC8088_GATE_TSTAT_Msk                  (0x01u << RC8088_GATE_TSTAT_Pos)
#define RC8088_GATE_FFT0_Pos                   (2)
#define RC8088_GATE_FFT0_Msk                   (0x01u << RC8088_GATE_FFT0_Pos)
#define RC8088_GATE_FFT1_Pos                   (3)
#define RC8088_GATE_FFT1_Msk                   (0x01u << RC8088_GATE_FFT1_Pos)
#define RC8088_GATE_EDMA_Pos                   (4)
#define RC8088_GATE_EDMA_Msk                   (0x01u << RC8088_GATE_EDMA_Pos)
#define RC8088_GATE_MIPI_Pos                   (5)
#define RC8088_GATE_MIPI_Msk                   (0x01u << RC8088_GATE_MIPI_Pos)
#define RC8088_GATE_WGEN_Pos                   (6)
#define RC8088_GATE_WGEN_Msk                   (0x01u << RC8088_GATE_WGEN_Pos)


/***************************************************/
/*-----------------------TEST----------------------*/
/***************************************************/
typedef struct{
 	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t txpbuf_clr_en:1;
			volatile uint32_t cbuf_clr_en:1;
			volatile uint32_t wbuf_clr_en:1;
			volatile uint32_t fbuf_clr_en:1;
			volatile uint32_t dbuf_clr_en:1;
			volatile uint32_t pbuf1_clr_en:1;
			volatile uint32_t pbuf0_clr_en:1;
			volatile uint32_t ipbuf1_clr_en:1;
			volatile uint32_t ipbuf0_clr_en:1;
			volatile const uint32_t RFU0:3;
			volatile uint32_t ecc_err_mode:1;
			volatile const uint32_t RFU1:3;
			volatile uint32_t ramp_80m_sel:1;
			volatile const uint32_t RFU2:15;
		}BIT;
	} TEST_CFG0;/*!< Offset: 0x78 (RW)*/
	volatile const  uint32_t RESERVED0[1];                  /*!< Offset: 0x79 (RFU)*/
 	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t txpbuf_ecc_err_1bit:1;
			volatile uint32_t cbuf_ecc_err_1bit:1;
			volatile uint32_t wbuf_ecc_err_1bit:1;
			volatile uint32_t fbuf_ecc_err_1bit:1;
			volatile uint32_t dbuf_ecc_err_1bit:1;
			volatile uint32_t pbuf_ecc_err_1bit:1;
			volatile uint32_t ibuf_ecc_err_1bit:1;
			volatile const uint32_t RFU0:1;
			volatile uint32_t txpbuf_ecc_err_2bit:1;
			volatile uint32_t cbuf_ecc_err_2bit:1;
			volatile uint32_t wbuf_ecc_err_2bit:1;
			volatile uint32_t fbuf_ecc_err_2bit:1;
			volatile uint32_t dbuf_ecc_err_2bit:1;
			volatile uint32_t pbuf_ecc_err_2bit:1;
			volatile uint32_t ibuf_ecc_err_2bit:1;
			volatile const uint32_t RFU1:17;
		}BIT;
	} TEST_STA0;/*!< Offset: 0x7A (RO-WC)*/
	volatile const  uint32_t RESERVED1[5];                  /*!< Offset: 0x7B (RFU)*/
} RC8088_TEST_st;

/*TEST_CFG*/
#define RC8088_TXPBUF_CLR_EN_Pos               (0)
#define RC8088_TXPBUF_CLR_EN_Msk               (0x01u << RC8088_TXPBUF_CLR_EN_Pos)
#define RC8088_CBUF_CLR_EN_Pos                 (1)
#define RC8088_CBUF_CLR_EN_Msk                 (0x01u << RC8088_CBUF_CLR_EN_Pos)
#define RC8088_WBUF_CLR_EN_Pos                 (2)
#define RC8088_WBUF_CLR_EN_Msk                 (0x01u << RC8088_WBUF_CLR_EN_Pos)
#define RC8088_FBUF_CLR_EN_Pos                 (3)
#define RC8088_FBUF_CLR_EN_Msk                 (0x01u << RC8088_FBUF_CLR_EN_Pos)
#define RC8088_DBUF_CLR_EN_Pos                 (4)
#define RC8088_DBUF_CLR_EN_Msk                 (0x01u << RC8088_DBUF_CLR_EN_Pos)
#define RC8088_PBUF1_CLR_EN_Pos                (5)
#define RC8088_PBUF1_CLR_EN_Msk                (0x01u << RC8088_PBUF1_CLR_EN_Pos)
#define RC8088_PBUF0_CLR_EN_Pos                (6)
#define RC8088_PBUF0_CLR_EN_Msk                (0x01u << RC8088_PBUF0_CLR_EN_Pos)
#define RC8088_IBUF1_CLR_EN_Pos                (7)
#define RC8088_IBUF1_CLR_EN_Msk                (0x01u << RC8088_IBUF1_CLR_EN_Pos)
#define RC8088_IBUF0_CLR_EN_Pos                (8)
#define RC8088_IBUF0_CLR_EN_Msk                (0x01u << RC8088_IBUF0_CLR_EN_Pos)
#define RC8088_ECC_ERR_MODE_Pos                (12)
#define RC8088_ECC_ERR_MODE_Msk                (0x01u << RC8088_ECC_ERR_MODE_Pos)
#define RC8088_RAMP_80M_SEL_Pos                (16)
#define RC8088_RAMP_80M_SEL_Msk                (0x01u << RC8088_RAMP_80M_SEL_Pos)

/*TEST_STA*/
#define RC8088_TXPBUF_ECC_ERR_1BIT_Pos         (0)
#define RC8088_TXPBUF_ECC_ERR_1BIT_Msk         (0x01u << RC8088_TXPBUF_ECC_ERR_1BIT_Pos)
#define RC8088_CBUF_ECC_ERR_1BIT_Pos           (1)
#define RC8088_CBUF_ECC_ERR_1BIT_Msk           (0x01u << RC8088_CBUF_ECC_ERR_1BIT_Pos)
#define RC8088_WBUF_ECC_ERR_1BIT_Pos           (2)
#define RC8088_WBUF_ECC_ERR_1BIT_Msk           (0x01u << RC8088_WBUF_ECC_ERR_1BIT_Pos)
#define RC8088_FBUF_ECC_ERR_1BIT_Pos           (3)
#define RC8088_FBUF_ECC_ERR_1BIT_Msk           (0x01u << RC8088_FBUF_ECC_ERR_1BIT_Pos)
#define RC8088_DBUF_ECC_ERR_1BIT_Pos           (4)
#define RC8088_DBUF_ECC_ERR_1BIT_Msk           (0x01u << RC8088_DBUF_ECC_ERR_1BIT_Pos)
#define RC8088_PBUF_ECC_ERR_1BIT_Pos           (5)
#define RC8088_PBUF_ECC_ERR_1BIT_Msk           (0x01u << RC8088_PBUF_ECC_ERR_1BIT_Pos)
#define RC8088_IBUF_ECC_ERR_1BIT_Pos           (6)
#define RC8088_IBUF_ECC_ERR_1BIT_Msk           (0x01u << RC8088_IBUF_ECC_ERR_1BIT_Pos)
#define RC8088_TXPBUF_ECC_ERR_2BIT_Pos         (8)
#define RC8088_TXPBUF_ECC_ERR_2BIT_Msk         (0x01u << RC8088_TXPBUF_ECC_ERR_2BIT_Pos)
#define RC8088_CBUF_ECC_ERR_2BIT_Pos           (9)
#define RC8088_CBUF_ECC_ERR_2BIT_Msk           (0x01u << RC8088_CBUF_ECC_ERR_2BIT_Pos)
#define RC8088_WBUF_ECC_ERR_2BIT_Pos           (10)
#define RC8088_WBUF_ECC_ERR_2BIT_Msk           (0x01u << RC8088_WBUF_ECC_ERR_2BIT_Pos)
#define RC8088_FBUF_ECC_ERR_2BIT_Pos           (11)
#define RC8088_FBUF_ECC_ERR_2BIT_Msk           (0x01u << RC8088_FBUF_ECC_ERR_2BIT_Pos)
#define RC8088_DBUF_ECC_ERR_2BIT_Pos           (12)
#define RC8088_DBUF_ECC_ERR_2BIT_Msk           (0x01u << RC8088_DBUF_ECC_ERR_2BIT_Pos)
#define RC8088_PBUF_ECC_ERR_2BIT_Pos           (13)
#define RC8088_PBUF_ECC_ERR_2BIT_Msk           (0x01u << RC8088_PBUF_ECC_ERR_2BIT_Pos)
#define RC8088_IBUF_ECC_ERR_2BIT_Pos           (14)
#define RC8088_IBUF_ECC_ERR_2BIT_Msk           (0x01u << RC8088_IBUF_ECC_ERR_2BIT_Pos)


/***************************************************/
/*-----------------------SF------------------------*/
/***************************************************/
typedef struct{
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t sf0_interFrameIdleTimeValueB:4;
			volatile uint32_t sf0_interFrameIdleTimeScaleB:2;
			volatile const uint32_t RFU0:2;
			volatile uint32_t sf0_profileNumB:8;
			volatile uint32_t sf0_profileNumA:8;
			volatile uint32_t sf0_profileLoopNum:6;
			volatile uint32_t sf0_profileLoopInf:1;
			volatile const uint32_t RFU1:1;
		}BIT;
	} SF_CFG0;/*!< Offset: 0x80 (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t sf1_interFrameIdleTimeValueB:4;
			volatile uint32_t sf1_interFrameIdleTimeScaleB:2;
			volatile const uint32_t RFU:2;
			volatile uint32_t sf1_profileNumB:8;
			volatile uint32_t sf1_profileNumA:8;
			volatile uint32_t sf1_profileLoopNum:6;
			volatile uint32_t sf1_profileLoopInf:1;
			volatile uint32_t sf1_valid:1;
		}BIT;
	} SF_CFG1;/*!< Offset: 0x81 (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t sf2_interFrameIdleTimeValueB:4;
			volatile uint32_t sf2_interFrameIdleTimeScaleB:2;
			volatile const uint32_t RFU:2;
			volatile uint32_t sf2_profileNumB:8;
			volatile uint32_t sf2_profileNumA:8;
			volatile uint32_t sf2_profileLoopNum:6;
			volatile uint32_t sf2_profileLoopInf:1;
			volatile uint32_t sf2_valid:1;
		}BIT;
	} SF_CFG2;/*!< Offset: 0x82 (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t sf3_interFrameIdleTimeValueB:4;
			volatile uint32_t sf3_interFrameIdleTimeScaleB:2;
			volatile const uint32_t RFU:2;
			volatile uint32_t sf3_profileNumB:8;
			volatile uint32_t sf3_profileNumA:8;
			volatile uint32_t sf3_profileLoopNum:6;
			volatile uint32_t sf3_profileLoopInf:1;
			volatile uint32_t sf3_valid:1;
		}BIT;
	} SF_CFG3;/*!< Offset: 0x83 (RW)*/
	volatile const  uint32_t RESERVED[12];                  /*!< Offset: 0x84 (RFU)*/
} RC8088_SF_st;

/*SF CFG0*/
#define RC8088_SF0_INTERFRAMEIDLEVALUEB_Pos    (0)
#define RC8088_SF0_INTERFRAMEIDLEVALUEB_Msk    (0x0Fu << RC8088_SF0_INTERFRAMEIDLEVALUEB_Pos)
#define RC8088_SF0_INTERFRAMEIDLESCALEB_Pos    (4)
#define RC8088_SF0_INTERFRAMEIDLESCALEB_Msk    (0x03u << RC8088_SF0_INTERFRAMEIDLESCALEB_Pos)
#define RC8088_SF0_PROFILENUMB_Pos             (8)
#define RC8088_SF0_PROFILENUMB_Msk             (0xFFu << RC8088_SF0_PROFILENUMB_Pos)
#define RC8088_SF0_PROFILENUMA_Pos             (16)
#define RC8088_SF0_PROFILENUMA_Msk             (0xFFu << RC8088_SF0_PROFILENUMA_Pos)
#define RC8088_SF0_PROFILELOOPNUM_Pos          (24)
#define RC8088_SF0_PROFILELOOPNUM_Msk          (0x3Fu << RC8088_SF0_PROFILELOOPNUM_Pos)
#define RC8088_SF0_PROFILELOOPINF_Pos          (30)
#define RC8088_SF0_PROFILELOOPINF_Msk          (0x01u << RC8088_SF0_PROFILELOOPINF_Pos)

/*SF CFG1*/
#define RC8088_SF1_INTERFRAMEIDLEVALUEB_Pos    (0)
#define RC8088_SF1_INTERFRAMEIDLEVALUEB_Msk    (0x0Fu << RC8088_SF1_INTERFRAMEIDLEVALUEB_Pos)
#define RC8088_SF1_INTERFRAMEIDLESCALEB_Pos    (4)
#define RC8088_SF1_INTERFRAMEIDLESCALEB_Msk    (0x03u << RC8088_SF1_INTERFRAMEIDLESCALEB_Pos)
#define RC8088_SF1_PROFILENUMB_Pos             (8)
#define RC8088_SF1_PROFILENUMB_Msk             (0xFFu << RC8088_SF1_PROFILENUMB_Pos)
#define RC8088_SF1_PROFILENUMA_Pos             (16)
#define RC8088_SF1_PROFILENUMA_Msk             (0xFFu << RC8088_SF1_PROFILENUMA_Pos)
#define RC8088_SF1_PROFILELOOPNUM_Pos          (24)
#define RC8088_SF1_PROFILELOOPNUM_Msk          (0x3Fu << RC8088_SF1_PROFILELOOPNUM_Pos)
#define RC8088_SF1_PROFILELOOPINF_Pos          (30)
#define RC8088_SF1_PROFILELOOPINF_Msk          (0x01u << RC8088_SF1_PROFILELOOPINF_Pos)
#define RC8088_SF1_VALID_Pos                   (31)
#define RC8088_SF1_VALID_Msk                   (0x01u << RC8088_SF1_VALID_Pos)

/*SF CFG2*/
#define RC8088_SF2_INTERFRAMEIDLEVALUEB_Pos    (0)
#define RC8088_SF2_INTERFRAMEIDLEVALUEB_Msk    (0x0Fu << RC8088_SF2_INTERFRAMEIDLEVALUEB_Pos)
#define RC8088_SF2_INTERFRAMEIDLESCALEB_Pos    (4)
#define RC8088_SF2_INTERFRAMEIDLESCALEB_Msk    (0x03u << RC8088_SF2_INTERFRAMEIDLESCALEB_Pos)
#define RC8088_SF2_PROFILENUMB_Pos             (8)
#define RC8088_SF2_PROFILENUMB_Msk             (0xFFu << RC8088_SF2_PROFILENUMB_Pos)
#define RC8088_SF2_PROFILENUMA_Pos             (16)
#define RC8088_SF2_PROFILENUMA_Msk             (0xFFu << RC8088_SF2_PROFILENUMA_Pos)
#define RC8088_SF2_PROFILELOOPNUM_Pos          (24)
#define RC8088_SF2_PROFILELOOPNUM_Msk          (0x3Fu << RC8088_SF2_PROFILELOOPNUM_Pos)
#define RC8088_SF2_PROFILELOOPINF_Pos          (30)
#define RC8088_SF2_PROFILELOOPINF_Msk          (0x01u << RC8088_SF2_PROFILELOOPINF_Pos)
#define RC8088_SF2_VALID_Pos                   (31)
#define RC8088_SF2_VALID_Msk                   (0x01u << RC8088_SF2_VALID_Pos)

/*SF CFG3*/
#define RC8088_SF3_INTERFRAMEIDLEVALUEB_Pos    (0)
#define RC8088_SF3_INTERFRAMEIDLEVALUEB_Msk    (0x0Fu << RC8088_SF3_INTERFRAMEIDLEVALUEB_Pos)
#define RC8088_SF3_INTERFRAMEIDLESCALEB_Pos    (4)
#define RC8088_SF3_INTERFRAMEIDLESCALEB_Msk    (0x03u << RC8088_SF3_INTERFRAMEIDLESCALEB_Pos)
#define RC8088_SF3_PROFILENUMB_Pos             (8)
#define RC8088_SF3_PROFILENUMB_Msk             (0xFFu << RC8088_SF3_PROFILENUMB_Pos)
#define RC8088_SF3_PROFILENUMA_Pos             (16)
#define RC8088_SF3_PROFILENUMA_Msk             (0xFFu << RC8088_SF3_PROFILENUMA_Pos)
#define RC8088_SF3_PROFILELOOPNUM_Pos          (24)
#define RC8088_SF3_PROFILELOOPNUM_Msk          (0x3Fu << RC8088_SF3_PROFILELOOPNUM_Pos)
#define RC8088_SF3_PROFILELOOPINF_Pos          (30)
#define RC8088_SF3_PROFILELOOPINF_Msk          (0x01u << RC8088_SF3_PROFILELOOPINF_Pos)
#define RC8088_SF3_VALID_Pos                   (31)
#define RC8088_SF3_VALID_Msk                   (0x01u << RC8088_SF3_VALID_Pos)


/***************************************************/
/*-------------------PROFILE MAN-------------------*/
/***************************************************/
typedef struct{
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t profile_man_vld:1;
			volatile const uint32_t RFU:31;
		}BIT;	
	} ProfileMan_CFG0;/*!< Offset: 0x90 (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t ramp_a_time:16;
			volatile uint32_t ramp_a_inc:16;
		}BIT;	
	} ProfileMan_CFG1;/*!< Offset: 0x91 (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t ramp_b_time:16;
			volatile uint32_t ramp_b_inc:16;
		}BIT;	
	} ProfileMan_CFG2;/*!< Offset: 0x92 (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t ramp_c_time:16;
			volatile uint32_t ramp_c_inc:16;
		}BIT;	
	} ProfileMan_CFG3;/*!< Offset: 0x93 (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t startFreq:32;
		}BIT;	
	} ProfileMan_CFG4;/*!< Offset: 0x94 (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t txEn:8;
			volatile uint32_t adcRma:16;
			volatile const uint32_t RFU:8;
		}BIT;	
	} ProfileMan_CFG5;/*!< Offset: 0x95 (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t tx3Phase:8;
			volatile uint32_t tx2Phase:8;
			volatile uint32_t tx1Phase:8;
			volatile uint32_t tx0Phase:8;
		}BIT;	
	} ProfileMan_CFG6;/*!< Offset: 0x96 (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t tx7Phase:8;
			volatile uint32_t tx6Phase:8;
			volatile uint32_t tx5Phase:8;
			volatile uint32_t tx4Phase:8;
		}BIT;	
	} ProfileMan_CFG7;/*!< Offset: 0x97 (RW)*/
	union
	{
		volatile uint32_t WORD;
		struct
		{
			volatile uint32_t loopNum:7;
			volatile uint32_t loopInf:1;
			volatile uint32_t pa_en_maskC:1;
			volatile uint32_t pa_en_maskB:1;
			volatile uint32_t pa_en_maskA:1;
			volatile const uint32_t RFU0:1;
			volatile uint32_t pll_acc_maskC:1;
			volatile uint32_t pll_acc_maskB:1;
			volatile uint32_t pll_acc_maskA:1;
			volatile const uint32_t RFU1:1;
			volatile uint32_t ramp_sycn_maskC:1;
			volatile uint32_t ramp_sycn_maskB:1;
			volatile uint32_t ramp_sycn_maskA:1;
			volatile const uint32_t RFU2:13;
		}BIT;	
	} ProfileMan_CFG8;/*!< Offset: 0x98 (RW)*/
} RC8088_ProfileMan_st;



/*PROFILE MAN CFG0*/
#define RC8088_PROFILE_MAN_VLD_Pos             (0)
#define RC8088_PROFILE_MAN_VLD_Msk             (0x01u << RC8088_PROFILE_MAN_VLD_Pos)

/*PROFILE MAN CFG1*/
#define RC8088_RAMP_A_TIME_Pos                 (0)
#define RC8088_RAMP_A_TIME_Msk                 (0xFFFFu << RC8088_RAMP_A_TIME_Pos)
#define RC8088_RAMP_A_INC_Pos                  (16)
#define RC8088_RAMP_A_INC_Msk                  (0xFFFFu << RC8088_RAMP_A_INC_Pos)

/*PROFILE MAN CFG2*/
#define RC8088_RAMP_B_TIME_Pos                 (0)
#define RC8088_RAMP_B_TIME_Msk                 (0xFFFFu << RC8088_RAMP_B_TIME_Pos)
#define RC8088_RAMP_B_INC_Pos                  (16)
#define RC8088_RAMP_B_INC_Msk                  (0xFFFFu << RC8088_RAMP_B_INC_Pos)

/*PROFILE MAN CFG3*/
#define RC8088_RAMP_C_TIME_Pos                 (0)
#define RC8088_RAMP_C_TIME_Msk                 (0xFFFFu << RC8088_RAMP_C_TIME_Pos)
#define RC8088_RAMP_C_INC_Pos                  (16)
#define RC8088_RAMP_C_INC_Msk                  (0xFFFFu << RC8088_RAMP_C_INC_Pos)

/*PROFILE MAN CFG4*/
#define RC8088_STARTFREQ_Pos                   (0)
#define RC8088_STARTFREQ_Msk                   (0xFFFFFFFFu << RC8088_STARTFREQ_Pos)

/*PROFILE MAN CFG5*/
#define RC8088_TXEN_Pos                        (0)
#define RC8088_TXEN_Msk                        (0xFFu << RC8088_TXEN_Pos)
#define RC8088_ADCRMA_Pos                      (8)
#define RC8088_ADCRMA_Msk                      (0xFFFFu << RC8088_ADCRMA_Pos)

/*PROFILE MAN CFG6*/ 
#define RC8088_TX3PHASE_Pos                    (0)
#define RC8088_TX3PHASE_Msk                    (0xFFu << RC8088_TX3PHASE_Pos)
#define RC8088_TX2PHASE_Pos                    (8)
#define RC8088_TX2PHASE_Msk                    (0xFFu << RC8088_TX2PHASE_Pos)
#define RC8088_TX1PHASE_Pos                    (16)
#define RC8088_TX1PHASE_Msk                    (0xFFu << RC8088_TX1PHASE_Pos)
#define RC8088_TX0PHASE_Pos                    (24)
#define RC8088_TX0PHASE_Msk                    (0xFFu << RC8088_TX0PHASE_Pos)

/*PROFILE MAN CFG7*/
#define RC8088_TX7PHASE_Pos                    (0)
#define RC8088_TX7PHASE_Msk                    (0xFFu << RC8088_TX7PHASE_Pos)
#define RC8088_TX6PHASE_Pos                    (8)
#define RC8088_TX6PHASE_Msk                    (0xFFu << RC8088_TX6PHASE_Pos)
#define RC8088_TX5PHASE_Pos                    (16)
#define RC8088_TX5PHASE_Msk                    (0xFFu << RC8088_TX5PHASE_Pos)
#define RC8088_TX4PHASE_Pos                    (24)
#define RC8088_TX4PHASE_Msk                    (0xFFu << RC8088_TX4PHASE_Pos)

/*PROFILE MAN CFG8*/
#define RC8088_LOOPNUM_Pos                     (0)
#define RC8088_LOOPNUM_Msk                     (0x7Fu << RC8088_LOOPNUM_Pos)
#define RC8088_LOOPINF_Pos                     (7)
#define RC8088_LOOPINF_Msk                     (0x01u << RC8088_LOOPINF_Pos)
#define RC8088_PA_EN_MASKC_Pos                 (8)
#define RC8088_PA_EN_MASKC_Msk                 (0x01u << RC8088_PA_EN_MASKC_Pos)
#define RC8088_PA_EN_MASKB_Pos                 (9)
#define RC8088_PA_EN_MASKB_Msk                 (0x01u << RC8088_PA_EN_MASKB_Pos)
#define RC8088_PA_EN_MASKA_Pos                 (10)
#define RC8088_PA_EN_MASKA_Msk                 (0x01u << RC8088_PA_EN_MASKA_Pos)
#define RC8088_PLL_ACC_MASKC_Pos               (12)
#define RC8088_PLL_ACC_MASKC_Msk               (0x01u << RC8088_PLL_ACC_MASKC_Pos)
#define RC8088_PLL_ACC_MASKB_Pos               (13)
#define RC8088_PLL_ACC_MASKB_Msk               (0x01u << RC8088_PLL_ACC_MASKB_Pos)
#define RC8088_PLL_ACC_MASKA_Pos               (14)
#define RC8088_PLL_ACC_MASKA_Msk               (0x01u << RC8088_PLL_ACC_MASKA_Pos)
#define RC8088_RAMP_SYNC_MASKC_Pos             (16)
#define RC8088_RAMP_SYNC_MASKC_Msk             (0x01u << RC8088_RAMP_SYNC_MASKC_Pos)
#define RC8088_RAMP_SYNC_MASKB_Pos             (17)
#define RC8088_RAMP_SYNC_MASKB_Msk             (0x01u << RC8088_RAMP_SYNC_MASKB_Pos)
#define RC8088_RAMP_SYNC_MASKA_Pos             (18)
#define RC8088_RAMP_SYNC_MASKA_Msk             (0x01u << RC8088_RAMP_SYNC_MASKA_Pos)


/***************************************************/
/*--------------------REG ADDR---------------------*/
/***************************************************/
#define RC8088_ESR0_ADDR            (0x64 << 2)
#define RC8088_REG_CRC_ADDR         (0x200 << 2)

/***************************************************/
/*----------------------SRAM-----------------------*/
/***************************************************/
#define RC8088_IBUFF0_CP                       0x0000u
#define RC8088_IBUFF0_CQ0                      0x0008u
#define RC8088_IBUFF0_CQ12                     0x0040u
#define RC8088_IBUFF0_END                      0x007Fu
#define RC8088_PBUFF0_BASE                     0x1000u
#define RC8088_PBUFF0_END                      0x17FFu
#define RC8088_DBUFF0_BASE                     0x2000u
#define RC8088_DBUFF1_BASE                     0x2100u
#define RC8088_DBUFF2_BASE                     0x2200u
#define RC8088_DBUFF3_BASE                     0x2300u
#define RC8088_DBUFF_END                       0x23FFu

#define RC8088_IBUFF1_CP                       0x8000u
#define RC8088_IBUFF1_CQ0                      0x8008u
#define RC8088_IBUFF1_CQ12                     0x8040u
#define RC8088_IBUFF1_END                      0x807Fu
#define RC8088_PBUFF1_BASE                     0x9000u
#define RC8088_PBUFF1_END                      0x97FFu
#define RC8088_CBUFF_BASE                      0xD000u
#define RC8088_CBUFF_END                       0xD1FFu
#define RC8088_TXBUFF_BASE                     0xD400u
#define RC8088_TXBUFF_END                      0xD47Fu
#define RC8088_FBUFF0_BASE                     0xE000u
#define RC8088_FBUFF1_BASE                     0xE200u
#define RC8088_FBUFF_END                       0xE3FFu
#define RC8088_WBUFF_BASE                      0xE800u
#define RC8088_WBUFF_END                       0xE87Fu


/***************************************************/
/*-------------------REG ADDR----------------------*/
/***************************************************/
#define  REG_ANA_STA0                          0x0000
#define  REG_ANA_STA1                          0x0004
#define  REG_ANA_STA2						   0x0008
#define  REG_ANA_STA3						   0x000C
//RESERVED0[12]
#define  REG_ANA_CFG00						   0x0040
#define  REG_ANA_CFG01						   0x0044
#define  REG_ANA_CFG02						   0x0048
#define  REG_ANA_CFG03						   0x004C
#define  REG_ANA_CFG04						   0x0050
#define  REG_ANA_CFG05						   0x0054
#define  REG_ANA_CFG06						   0x0058
#define  REG_ANA_CFG07						   0x005C
#define  REG_ANA_CFG08						   0x0060
#define  REG_ANA_CFG09						   0x0064
#define  REG_ANA_CFG10						   0x0068
#define  REG_ANA_CFG11						   0x006C
#define  REG_ANA_CFG12						   0x0070
#define  REG_ANA_CFG13						   0x0074
#define  REG_ANA_CFG14						   0x0078
#define  REG_ANA_CFG15						   0x007C
#define  REG_ANA_CFG16						   0x0080
#define  REG_ANA_CFG17						   0x0084
#define  REG_ANA_CFG18						   0x0088
#define  REG_ANA_CFG19						   0x008C
#define  REG_ANA_CFG20						   0x0090
#define  REG_ANA_CFG21						   0x0094
#define  REG_ANA_CFG22						   0x0098
#define  REG_ANA_CFG23						   0x009C
#define  REG_ANA_CFG24						   0x00A0
#define  REG_ANA_CFG25						   0x00A4
//RESERVED1[5]
#define  REG_COM_CFG1						   0x00BC
#define  REG_PREP_CFG0						   0x00C0
#define  REG_PREP_CFG1						   0x00C4
#define  REG_PREP_CFG2						   0x00C8
#define  REG_PREP_CFG3						   0x00CC
#define  REG_PREP_CFG4						   0x00D0
#define  REG_PREP_CFG5						   0x00D4
#define  REG_PREP_STA0						   0x00D8
//RESERVED1[5]
#define  REG_P10_CFG0						   0x00F0
#define  REG_P10_CFG1						   0x00F4
//RESERVED1[2]
#define  REG_DMA_CFG0						   0x0100
#define  REG_DMA_CFG1						   0x0104
#define  REG_DMA_CFG2						   0x0108
#define  REG_DMA_CFG3						   0x010C
//RESERVED1[4]
#define  REG_FFT_CFG0						   0x0120
#define  REG_FFT_CFG1						   0x0124
#define  REG_FFT_STA0						   0x0128
//RESERVED1[5]
#define  REG_MIPI_CFG0						   0x0140
#define  REG_MIPI_CFG1						   0x0144
#define  REG_MIPI_CFG2						   0x0148
#define  REG_MIPI_CFG3						   0x014C
#define  REG_MIPI_CFG4						   0x0150
//RESERVED1[3]
#define  REG_MIPI_STA0						   0x0160
#define  REG_MIPI_STA1						   0x0164
//RESERVED1[6]
#define  REG_IMR							   0x0180
#define  REG_EMR0							   0x0184
#define  REG_EMR1							   0x0188
#define  REG_ISR							   0x018C
#define  REG_ESR0							   0x0190
#define  REG_ESR1							   0x0194
//RESERVED1[10]
#define  REG_OP_GATE						   0x01C0
//RESERVED1[7]
#define  REG_TEST_CFG0						   0x01E0
//RESERVED1[1]
#define  REG_TEST_STA0						   0x01E8
//RESERVED1[5]
#define  REG_SF_CFG0						   0x0200
#define  REG_SF_CFG1						   0x0204
#define  REG_SF_CFG2						   0x0208
#define  REG_SF_CFG3						   0x020C
//RESERVED1[12]
#define  REG_PROF_MAN_CFG0					   0x0240
#define  REG_PROF_MAN_CFG1					   0x0244
#define  REG_PROF_MAN_CFG2					   0x0248
#define  REG_PROF_MAN_CFG3					   0x024C
#define  REG_PROF_MAN_CFG4					   0x0250
#define  REG_PROF_MAN_CFG5					   0x0254
#define  REG_PROF_MAN_CFG6					   0x0258
#define  REG_PROF_MAN_CFG7					   0x025C
#define  REG_PROF_MAN_CFG8					   0x0260
#define  REG_CRC_CHECK_RSLT					   0x0800




typedef struct{
	RC8088_ANA_st             ANA;          //RC8088_BASE
	RC8088_COMMON_st          COMMON;
	RC8088_PREP_st            PREP;
	RC8088_P10_st             P10;
	RC8088_DMA_st             DMA;
	RC8088_FFT_st             FFT;
	RC8088_MIPI_st            MIPI;
	RC8088_INT_st             INT;
	RC8088_OpGate_st          OP_GATE;
	RC8088_TEST_st            TEST;
	RC8088_SF_st              SF;
	RC8088_ProfileMan_st      PROFILE_MAN;
} RC8088_RegCfg_st;


enum RC8088_IFMode
{
	RC8088_SPI_MODE = 0,
	RC8088_QSPI_MODE
};

enum RC8088_EndianMode
{
	RC8088_L_END = 0,
	RC8088_B_END
};

enum RC8088_SPI_DEV
{
	RC8088_RF_0 =0,		// far antenna;
	RC8088_RF_1,		// near antenna;
//	RC8088_RF_2,
//	RC8088_RF_3
};

typedef struct
{
	uint8_t IFMOD;            //InterFace mode 0:SPI 1:QSPI
	uint8_t ENDIAN;           //Endian mode 0:lttle endian  1:big endian
	uint8_t	SPI_RF_DEV;		  // 0--far antenna; 1--near antenna
} RC8088_RWCfg_st;

typedef enum 
{
	RW_OK = 0,
	RW_LEN_ERR,
	RW_IF_ERR,
	RW_CRC_ERR,
	RW_RTN_ERR,
	REG_CRC_ERR
} RC8088_OperateStatus;


typedef struct
{
	union
	{
		uint32_t DATA32[4];
		uint8_t DATA8[16];
	};
} RC8088_MemDat_st;


typedef struct
{

	union
	{
		uint32_t DATA32;
		uint8_t DATA8[4];
	};
} RC8088_RegDat_st;



enum RC8088_OpGateStatus
{
	ON = 0,
	OFF
};

enum RC8088_IntStatus
{
	Enable = 0,
	Disable
};
typedef struct{
	int16_t chX_dc;
    uint16_t chX_abs_max;
    uint16_t chX_abs_mean;
    uint16_t chX_diff_mean;
} RC8088_CQ0_TIMING_st;
typedef struct{
	uint32_t fft_dataX_cur_max;
    uint32_t fft_dataX_total_max;
} RC8088_CQ0_FFT_st;
typedef struct{
	RC8088_CQ0_TIMING_st RX[8];
    RC8088_CQ0_FFT_st FFT[4];
} RC8088_CQ0_st;

RC8088_OperateStatus  HAL_RC8088_ClrAll(RC8088_RWCfg_st *pCfg);
RC8088_OperateStatus  HAL_RC8088_ClrAllStatus(RC8088_RWCfg_st *pCfg);
RC8088_OperateStatus  HAL_RC8088_ClrWgen(RC8088_RWCfg_st *pCfg);
RC8088_OperateStatus  HAL_RC8088_ClrMipi(RC8088_RWCfg_st *pCfg);
RC8088_OperateStatus  HAL_RC8088_ClrEdma(RC8088_RWCfg_st *pCfg);
RC8088_OperateStatus  HAL_RC8088_ClrFFT(RC8088_RWCfg_st *pCfg);
RC8088_OperateStatus  HAL_RC8088_ClrPrep(RC8088_RWCfg_st *pCfg);
RC8088_OperateStatus  HAL_RC8088_ClrReg(RC8088_RWCfg_st *pCfg);
RC8088_OperateStatus  HAL_RC8088_ClrMem(RC8088_RWCfg_st *pCfg);

RC8088_OperateStatus  HAL_RC8088_TrigP10(RC8088_RWCfg_st *pCfg);
RC8088_OperateStatus  HAL_RC8088_TrigEdma(RC8088_RWCfg_st *pCfg);

RC8088_OperateStatus  HAL_RC8088_RegCrcCheck(RC8088_RWCfg_st *pCfg);
RC8088_OperateStatus  HAL_RC8088_WaveStart(RC8088_RWCfg_st *pCfg);
RC8088_OperateStatus  HAL_RC8088_WaveStop(RC8088_RWCfg_st *pCfg);
RC8088_OperateStatus  HAL_RC8088_BigEndian(RC8088_RWCfg_st *pCfg);
RC8088_OperateStatus  HAL_RC8088_LittleEndian(RC8088_RWCfg_st *pCfg);

RC8088_OperateStatus HAL_RC8088_Init(RC8088_RWCfg_st *RC8088_RW_Cfg);

RC8088_OperateStatus HAL_RC8088_RdReg(RC8088_RWCfg_st *pCfg, uint16_t pRegAddr, RC8088_RegDat_st *pu32ReadRegData, uint16_t u16Len);
RC8088_OperateStatus HAL_RC8088_RdMem(RC8088_RWCfg_st *pCfg, uint16_t u16MemAddr, RC8088_MemDat_st *pRdMemData, uint16_t u16Len);
RC8088_OperateStatus HAL_RC8088_WrReg(RC8088_RWCfg_st *pCfg, uint16_t pRegAddr,void *pRegDat, uint16_t u16Len);
RC8088_OperateStatus HAL_RC8088_WrMem(RC8088_RWCfg_st *pCfg, uint16_t u16MemAddr, RC8088_MemDat_st *pWrMemData, uint16_t u16Len);

uint32_t HAL_RC8088_GetInt(RC8088_RWCfg_st *pCfg, uint16_t pRegAddr);
RC8088_OperateStatus HAL_RC8088_ClrAllInt(RC8088_RWCfg_st *pCfg, RC8088_INT_st *pRegAddr);
RC8088_OperateStatus HAL_RC8088_ClrESR0Int(RC8088_RWCfg_st *pCfg, RC8088_INT_st *pRegAddr);
RC8088_OperateStatus HAL_RC8088_ClrESR1Int(RC8088_RWCfg_st *pCfg, RC8088_INT_st *pRegAddr);
RC8088_OperateStatus HAL_RC8088_CaliberADC(RC8088_RWCfg_st *pCfg, RC8088_ANA_st *pRegAddr, uint8_t u8Channel);
RC8088_OperateStatus HAL_RC8088_profileManFreqTest(RC8088_RWCfg_st *pCfg, RC8088_RegCfg_st *pRegAddr,uint32_t startFreq);
RC8088_OperateStatus HAL_RC8088_CaliberVCO(RC8088_RWCfg_st *pCfg, RC8088_RegCfg_st *pRegAddr,uint32_t startFreq,uint32_t stopFreq);
RC8088_OperateStatus HAL_RC8088_RX_DC_Calib(RC8088_RWCfg_st *pCfg, RC8088_RegCfg_st *pRegAddr);
RC8088_OperateStatus HAL_RC8088_ADC_SYNC_CLK_Calib(RC8088_RWCfg_st *pCfg, RC8088_RegCfg_st *pRegAddr,uint32_t startFreq);
RC8088_OperateStatus HAL_RC8088_RC_Corner_Calib(RC8088_RWCfg_st *pCfg, RC8088_RegCfg_st *pRegAddr);
#endif
